`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Westlake University
// Engineer: shenziyang@westlake.edu.cn 
// 
// Create Date: 2021/11/23 20:32:48
// Design Name: HW3
// Module Name: tb_shift_register_8bit
// Project Name: hw3
// Target Devices: VCU118
// Tool Versions: vivado 2020.1
// Description: testbench for Homework 3
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_shift_register_8bit();
    reg clk;
    reg dir;
    reg rst_n;
    wire [7:0] D;

    initial begin
        dir <= 0;//默认右移
        rst_n <= 1;
        # 10 rst_n <= 0;
    end
    always begin
        #5 clk = 1;#5 clk = 0;
    end

shift_register_8bit inst_shift_register_8bit(clk, dir, rst_n, D);
endmodule
